Dear all,


is it possible to use SpectreRF to simulate the closed-loop PLL phase noise performance at transistor level?
Just assuming that simulation time is no issue, has anyone experience on this?

Is it difficult to get convergence? I know for example that EldoRF has difficulty converging when a LC-VCO and a subsequent CML + asynchronous FF-style divider are combined, so I never even tried full PLL simulation with it...


Kind Regards

Peter

Dear Ken,


thanks for your comment.

If I understood your comment right, you expect SpectreRF to converge as long as there's a periodic solution, which would indeed be an improvement over EldoRF.

Do you think that a reference input signal that is dithered with jitter poses problems for SpectreRF? The goal would be to verify the input CLK jitter attenuation using such a set-up.

Kind Regards

Peter