Hi, Peter and Carl,
That is a really interesting topic. I have been thinking it over from I studied ADC and PLL. I was perplexed at the begining. Deterministic jitter, random jitter, long term jitter, short term jitter, period jitter, cycle-to-cycle jitter .... There are a lot of terms for those guys who design a PLL. However, the jitter requirement for ADC is generally stated like jitter or rms jitter. So Peter said as below.
Quote:Now let's turn our attention to the ADC CLK jitter requirement: all papers just mention 'dt', without describing the nature of the jitter.
Statements like 'ADC CLK Jitter should be better than 10ps' etc. are made.
Obviously, there is a gap between the engineers who design PLLs and those who design ADCs. However, the definitions of jitter are so complex that I will clarify here before I talk about the jitter requirement for ADC.
Why Peter said DJ and RJ Carl said edge jitter, period jitter, cycle-to-cycle jitter?
In fact DJ and RJ are not terms used for a clock generator, but for a transmitter in data communication like LVDS or Serdes. The output of a transmitter is binary stream, not a clock. :) The DJ and RJ of a transmitter is often tested using a Pseudo Random Binary Stream (PRBS) source. So the DJ is composed of sinusoidal jitter (low frequency), data dependent jitter (ISI), and Duty Cycle Distortion. They are caused by some deterministic source, often strongly related to the circuit topology. We care about pk-pk value of DJ. RJ is due to the clock source in the transmitter. It makes the edge of the binary stream goes ahead or lag the ideal point randomly. It is mainly caused by thermal noise. The measured pk-pk value of RJ depends on how long you measure the output of a transmitter. So we measure its rms value. Then according to the required BER, we decide how many times rms value of RJ is added with DJ. So we have the formula TJ=DJ+n*RJ. Normally, n is not equal to 1.
The long term-jitter, short-term jitter, period jtter are used to characterize a clock. For clock of ADCs, I agree with Carl on the statements below.
Quote:Jitter is just a consequence of the period of the clock having some amount of variability. Long-term jitter is not an issue, because the clocks are generated in a feedback loop (some kind of PLL usually) so the average period over time is constant. What is troublesome from an SNR standpoint in an ADC is the instantaneous variations between periods. So, I would call edge jitter, period jitter and cycle-to-cycle jitter synonyms.
Furthermore, we often lock the phases of clock source and signal source when testing ADCs, thus the long term jitter is not important here.
Here I want to discuss cycle-to-cycle jitter and period jitter. Some literature use both names as synonyms. However, sometimes cycle-to-cycle jitter is not period jitter. For a spread-spectrum clock, which is often used on a PC motherboad to meet FCC EMI requirment, cycle-to-cycle jitter is the differnece between two consecutive cycles.
Any comments are welcomed.
Yawei