dandelion
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Hi SRF, Thanks for the help. Would you pls. see the questions and comments below? I need your help.
Dandelion, There are many reasons you can experience these types of failures, and I can see several possibilities based on your schematic. As I am not fully familiar with your design and process technology, take my comments with a grain of salt. I am guessing your NMOS failures indicate snapback breakdown. (best I can do without FA data) This is classic: the voltage is to high between the pad and the Vss connected to the failing NMOS source. I see its quite possible your NMOS has a source vss (GNDD) separate from the vss that the ESD diode is connected to (GNDA). This takes us to my first point. [Dandelion]yes, it is so. First: Though you stated you are using GNDD or GNDA as separate substrates, it is obvious you are not actively clamping them together. Separate ground domains need to be clamped together. Passive substrate resistance can help tremendously, but if the substrate is High-res or if the total area of P+ tap is not sufficient(especially for low-res epi processes), separate substrates may not conduct ESD currents enough, and active clamping is need. [Dandelion]We are using the 0.6um p-sub lightly-doped submicron cmos process.So, it should be high-res. Whenever you do any negative stresses on the digital IO, it will sink current from GNDA but what about parasitic current paths on GNDD? I imagine your digital output drivers are connected to GNDD (your failing NMOS's no doubt) though you were not explicit. I expect that this separation between the ESD substrate (GNDA) and the output driver Vss (GNDD) is likely causing problems...if they are not sufficiently clamped, which I do not know for certain. [Dandelion]I have a puzzle here. Even, we have actively clamps between the GNDD and GNDA, there is still most possibility for the voltage is too high between the pad and the Vss connected to the failing NMOS source, as you mentioned above. Any wrong misunderstanding for me? I did note that GNDD is clamped to VDDA which then clamps to GNDA, but this is not sufficient for substrate protection paths. [Dandelion]yes, we also think so. [Dandelion]In addition, we do another ESD test today when shorted the VDDD and VDDA together, GNDD and GNDA together, respectively. We do this test is to hope it pass, because they are in fact connected together in PCB. But, it failed again. The results showed that it is just contrary to the previous test. Still the same four pins failed. Three digital output pin which is the CMOS output and one analog pin. Three digital output pin did not pass the positive pulse to GNDA strike. And moreover, two of them did not pass the positive pulse to IO and one of them did not pass the negative pulse to IO.The analog pin did not pass the negative pulse of IO. That made us more puzzled. Because, this time, there should be no separation between the power. Second: The smaller diodes on the digital I/O are likely not helping. [Dandelion]I guess you mean the VDDD and GNDD pin, right? We did not reduce the diodes for I/O pins. Your concern is noise, but remember your diode may only have 0.5pF to 1pF capacitance. How much noise isolation did you gain by reducing the diodes? If you can not answer that question, than you probably made a very common decision/mistake in reducing the diodes, while not fully understanding what your noise boundaries/margins were. This is quite common and I would recommend you do a thorough noise analysis before deciding to reduce your diodes. (I see that you did estimate the noise swing, the question is did you estimate how much of that swing would be coupled across the diode?) If your impedances for GNDA/VDDA are low enough, you may be able to tolerate even significant large-signal current coupling across the diodes junction, as well as the purely capacitive coupling. (note even at 0.7V forward biased, most ESD devices are conducting less than 1mA current) [Dandelion]The switching noise coupling to the VDDA and GNDD is just one concern. Another concern is the VDDD and GNDD bounce will forwarded the diode and introduce the noise. If it have only ~mA current when conducting, i.e.5mV in 5V supply. It should be OK. We indeed made a mistake thoughtless.
Thirdly: Diodes handling positive currents are only one part of the ESD current path, the other is the power bus resistances and power clamps. These can actually have a greater influence on ESD performance of an I/O than the diodes themselves. I would review your power bus models and especially your power bus clamps. As far as I can tell, reverse biased diodes (I imagine it is really grounded gate MOS devices operating in snapback) are all you are using and I know for a fact that those are generally not sufficient (If you are really using gg MOS-snapback devices, which you really meant by the diodes (NMOS OR PMOS as your key states) on schematic, then note that some of your current paths are dependent on two or three snapback devices in series, plus diodes. This is just something to keep in mind). Also note that ggPMOS (I suspect this is what you are using for your VDDA to GNDD clamping based on the schematic) protection structures are typically very weak and almost useless. I would personally replace any of these with ggNMOS's. A few other comments: 1. Get some TLP data on
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