Dandelion,
    There are many reasons you can experience these types of failures, and I can see several possibilities based on your schematic.  As I am not fully familiar with your design and process technology, take my comments with a grain of salt.

I am guessing your NMOS failures indicate snapback breakdown.  (best I can do without FA data)
 This is classic: the voltage is to high between the pad and the Vss connected to the failing NMOS source.

I see its quite possible your NMOS has a source vss (GNDD) separate from the vss that the ESD diode is connected to (GNDA).  This takes us to my first point.

First:  Though you stated you are using GNDD or GNDA as separate substrates, it is obvious you are not actively clamping them together.  Separate ground domains need to be clamped together.  Passive substrate resistance can help tremendously, but if the substrate is High-res or if the total area of P+ tap is not sufficient(especially for low-res epi processes), separate substrates may not conduct ESD currents enough, and active clamping is need.

 Whenever you do any negative stresses on the digital IO, it will sink current from GNDA but what about parasitic current paths on GNDD?  I imagine your digital output drivers are connected to GNDD (your failing NMOS's no doubt) though you were not explicit.   I expect that this separation between the ESD substrate (GNDA) and the output driver Vss (GNDD) is likely causing problems...if they are not sufficiently clamped, which I do not know for certain.

I did note that GNDD is clamped to VDDA which then clamps to GNDA, but this is not sufficient for substrate protection paths.

Second:  The smaller diodes on the digital I/O are likely not helping.  Your concern is noise, but remember your diode may only have 0.5pF to 1pF capacitance.  How much noise isolation did you gain by reducing the diodes?  If you can not answer that question, than you probably made a very common decision/mistake in reducing the diodes, while not fully understanding what your noise boundaries/margins were.  This is quite common and I would recommend you do a thorough noise analysis before deciding to reduce your diodes.  (I see that you did estimate the noise swing, the question is did you estimate how much of that swing would be coupled across the diode?)  If your impedances for GNDA/VDDA are low enough, you may be able to tolerate even significant large-signal current coupling across the diodes junction, as well as the purely capacitive coupling.  (note even at 0.7V forward biased, most ESD devices are conducting less than 1mA current)

Thirdly: Diodes handling positive currents are only one part of the ESD current path, the other is the power bus resistances and power clamps.  These can actually have a greater influence on ESD performance of an I/O than the diodes themselves.   I would review your power bus models and especially your power bus clamps.  As far as I can tell, reverse biased diodes (I imagine it is really grounded gate MOS devices operating in snapback) are all you are using and I know for a fact that those are generally not sufficient (If you are really using gg MOS-snapback devices, which you really meant by the diodes (NMOS OR PMOS as your key states) on schematic, then note that some of your current paths are dependent on two or three snapback devices in series, plus diodes.  This is just something to keep in mind).  
Also note that ggPMOS (I suspect this is what you are using for your VDDA to GNDD clamping based on the schematic) protection structures are typically very weak and almost useless.  I would personally replace any of these with ggNMOS's.

A few other comments:

1. Get some TLP data on the failing pins as well as equivalent pins that are passing, for comparison. Take 2 curves for each pin, one referenced to GNDA, the other to GNDD.  This will give you a lot of insight into your protection strategy and structures.

2.  Do some CDM testing.  Your schematic indicates you may actually have a worse CDM (charge deice model) problem, and as CDM is much more reflective of modern manufacturing/assembly processes, you will want to know that data to ensure that you have no field returns from your customers.

That is the best I can offer at this time.  Hope it helps.
-SRF Tech

Hi, SRF,
We made the DC test for the second failed ESD chip. The test proved that it is still the NMOS transistor failed. We think your analysis on the 1st point is the cause of the ESD failure.

For the DOUT pin, we found although it did not pass the ESD test, just only one of them did not pass the 2000V for the three samples. It is better than the other two digital pins. We found the NMOS transistor have almost twice size of the other two digital pins.,

Now, we want to try to make some modification for our chip. We hope to use one or two metal fix. We have a check for our layout. We found what we can do is to add a diode between the GNDA and GNDD and increase the size of the NMOS transistor with dummy transistors around. We found that for the last stage inverter, the PMOS size is twice of the NMOS, we guess that’s why it can stand the 2000V zap. So we think the increased NMOS size can improve the ESD performance also. We hope to add two back to back diodes between the GNDA and GNDD, but we have only one from GNDA to GNDD in hand.

Would you see any risks in it?

BR
Thanks
Dandelion

What process node are you at? Your foundry will normally have a base design for ESD. You should put it on a few pads at least.

SRF, thanks for the detailed advice. BTW, Googling 'SRF Tech esd' doesn't get you, I need to type 'SRF Technologies esd'. Maybe invest in some AdWords?  :)

M.G.Rajan
www.eecalc.com