Hello All,

What is the easiest way to simulate the ft of a process in HSPICE. Any enlightment.

Tx

ic_engr

Note that fT uses an ideal current source excitation, so there is no time constant due to base/gate series resistance (unlike a voltage source excitation). Now the DC input resistance of a MOS transistor is obviously in the GOhm or TOhm range so you may ask why gate resistance is relevant. It's because there is a component of gate (poly) resistance that charges the extrinsic gate-drain capacitance.

fT is a good metric for classes of digital circuits that are entirely gm driven - a regenerative flip-flop is a good example. So, a frequency divider is an excellent circuit to leverage fT.

But if you're designing an LNA you must look at fmax, or some other bizarre metric that also involves the noise circles. It's very well to play safe and say look at both fT and fmax, but if you know what you're designing you can push your process.

M.G.Rajan
www.eecalc.com

fT does vary depending on bias.
fT quoted by foundries for a particular process are usually obtained given specific device size, current density, device temperature & supply/bias volatges (best choosen to give a nice high value). It is often the case that the designer will not bias devices for maximum fT, but for other performace paramters.
cheers
aw