Hi all,

I am trying to run an AMS Designer simulation involving pure verilog rtl and verilogAMS converted from a PLL schematic.

I have a weird problem: when I try to reset the charge pump inside of the PLL (either with a digital control pin or with a vpwl inside the schematic), the simulator hangs. I hold reset on at t=0 and then release it sometime later t>0. The simulation starts fine and runs until reset is released. It then runs for several hundred ns more. The simulation step size then decreases where it becomes 1 fs and then hangs.

Do any of you have some suggestions as to what is causing the problems?

Thanks,
southofthebay