Saran
Junior Member
Offline
Getting wiser by the second
Posts: 10
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I have a strange problem while simulating schematics consisting of verilog-ams models. I have created some simple Verilog-AMS models by choosing new cell view (verilog-ams - hdl editor). I put together a schematic in the composer schematic editor consisting of the verilog-ams modules or models. When I try to simulate this circuit in analog environement under spectre, it throws me an error saying that it is unable to descend in the ams view. creating a configuration in the hierarchy editor does not do any good. However, when I define the same models as verilog-a instead of verilog-ams when I create them using new cell view, the circuit simulates fine. Can somebody clarify what is happening?
maybe, I am doing something bizzare or is there a problem within cadence? Not that this affects me much because the circuits I am working with right now are pure analog. However, this is not seem right for me to ignore.
Thanks, Saran
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