I have a strange problem while simulating schematics consisting of verilog-ams models. I have created some simple Verilog-AMS models by choosing new cell view (verilog-ams - hdl editor). I put together a schematic in the composer schematic editor consisting of the verilog-ams modules or models. When I try to simulate this circuit in analog environement under spectre, it throws me an error saying that it is unable to descend in the ams view. creating a configuration in the hierarchy editor does not do any good. However, when I define the same models as verilog-a instead of verilog-ams when I create them using new cell view, the circuit simulates fine. Can somebody clarify what is happening?

maybe, I am doing something bizzare or is there a problem within cadence? Not that this affects me much because the circuits I am working with right now are pure analog. However, this is not seem right for me to ignore.

Thanks,
Saran

Oh da!!! That makes sense. Should have thought about that.

I had a small doubt. Syntactically, are verilog-AMS and verilog-a not the same? Except from verilog-ams sort of being the superset of verilog-a, is there any notable differences? For instance, if I build my analog models in verilog-a, and later I want to add mixed signal interfaces, how hard would it to be take the existing code and append it?

Thanks for the reply, Geoffrey.

Geoffrey didn't answer your Question..
Verilog-AMS is a super set of Verilog-A, Verilog and the mixed signal code.. .
or to put it the way the language is specified, Verilog-A is the ANALOG ONLY subset of verilog-AMS..
Basically in Verilog-AMS you can do everything you did in Verilog (this is the stuff spectre doesn't do)
+ everything you do in Spectre..

In verilog-A you can declare an electrical or wire node, but not a reg..
All the behavior has to happen in the "analog" block..
in Verilog-AMS you are allowed "reg" "wreal" and can put your behavior
in Assign statements, initial blocks, always blocks and declare tasks..
as WELL as have interaction between the electrical and regs, and regs and electricals
and an "analog" block..

jbd