I don't know if I am abusing Verilog-A...but, can't we specify both output voltages and currents in a block. For instance, in this oversimplified and incomplete model of a common source amplifier,

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ampSig = gain * (V(in) - dcoff);
V(out) <+ ampSig + vds;
I(out) <+ some previously computed value.

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When I run this sim in spectre, my voltage V(out) is what I am expecting to be..However I(out) returns zero. Is there anything horrible I am doing here? I am playing with Verilog-a modeling. This is a simple module with one input and output port (Common source amp).

Thanks,
Saran

Oh..I was just trying to write a test module. I had specified the voltage but I also wanted to see the drain current of the output transitor. I guess it was clear abuse of Verilog-a. I know I should have specified an intermediate node for that. Anyways, thanks for the response.