Saran
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Getting wiser by the second
Posts: 10
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I don't know if I am abusing Verilog-A...but, can't we specify both output voltages and currents in a block. For instance, in this oversimplified and incomplete model of a common source amplifier,
snip.. snip..
ampSig = gain * (V(in) - dcoff); V(out) <+ ampSig + vds; I(out) <+ some previously computed value.
snip.. snip..
When I run this sim in spectre, my voltage V(out) is what I am expecting to be..However I(out) returns zero. Is there anything horrible I am doing here? I am playing with Verilog-a modeling. This is a simple module with one input and output port (Common source amp).
Thanks, Saran
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