I have always struggled with this myself.  Over the last few years I have settled on measuring total power (not averaged) as a function of activity factor.  I usually also give a max power consumption which is the extracted full power with an activity factor of 100% as well as stand-by leakage current.  I am still uncertain as to what the benefit is in detailing the average or RMS power of an I/O buffer (though it is useful internally when considering Electro-migration reliability issues along your power rails and interconnect, in which case I do use average, but this is generally not a value that I publish in my design reviews or datasheets).  

Possibly some else has a different perspective?

Note that these comments mostly apply to standard push-pull CMOS buffers.  Serial interfaces (if using a current steering architecture) are a little easier to detail as they tend to have nice DC bias currents with little current (i.e.  read as 'power') variation as a function of signaling transitions.

CORRECTION:  I thought about it after I posted; current calculations for Electro-Migration issues depends on the process technology you are using, some use an extrapolated calculation based on Idc and capacitive loads, others use Irms or Iaveraged currents depending on the modeling.  Ergo my comment on the fact that I use the average for internal electro-migration is not entirely accurate.

Peter,
I am not certain we are discussing the same concept of transient power consumption.

Your comment about current leaving a voltage source and then returning (i.e changes direction) makes me think that you are looking at one of two options:  the power delivered into a capacitive load, where first it is charged up by the buffer and then it is discharged by the buffer; or more correctly maybe you are thinking of a buffer driving a load resistor tied to some VCM or VDD/2 where when driving high, our buffer sources current and when driving low we sink current... either way I am not sure exactly what you mean then by transient power consumption because this is the current moving in and out of the Buffer output, not necessarily the power consumed by the buffer.

My perspective on buffer power consumption was that I thought you meant the power consumed by a CMOS driver driving a capacitive/CMOS load... (I ignored external pull-up/down loads as that would be a system level power consumption question.  In this case, I am only concerned with the current sourced by my VDD supply to the buffer.  This current is only sourced when I drive a high value (as driving a 0 simply sinks current from the load capacitor into my VSS).  Ergo, my current is dependent how how often I drive that high value and that is why I tied it to activity factor.

So, I guess my question for you is, are we discussing the same buffer/topology/situation etc.?

-SRF Tech

I have a question from both SRF and Rajan.
SRF wrote:
In this case, I am only concerned with the current sourced by my VDD supply to the buffer.  This current is only sourced when I drive a high value (as driving a 0 simply sinks current from the load capacitor into my VSS)... my current is dependent how how often I drive that high value and that is why I tied it to activity factor.

I AM NOT CLEAR HERE. FROM THE PREVIOUS POSTS IT IS SAID THAT THE POWER IS GOING BACK TO VSS. BY MAKING THE ACTIVITY FACTOR AS 0.5 CAN WE ONLY CONSIDER THE CURRENT SOURCED TO BUFFER. WILL THE RESULT BE SAME IF I CONSIDER THE CURRENT SINKED TO VSS ALSO WITH ACTIVITY FACTOR 1.

Rajan:
I am gettng that for any push-pull amplifier or for a inverter the Power is calculated by avg current, which will be close to zero (except leakage current).

Please comment.

Bharat,
I think the discussion got confused regarding the situation in which power is being measured, so your question is not surprising.
As for your question, when a circuit is present, and power is being dissipated between VDD and VSS, as long as total current paths are accounted for, you can monitor the current flow into either VSS (When considering current sinking into VSS, ensure you are accounting for load currents as well as the buffer) or out of the VDD node, either way, you are measuring the flow of current at a given voltage, from this you calculate the power you are looking for  (DC, average, RMS, etc).
-SRF Tech