I put together a simple circuit to see if pnoise jitter gives reasonable results.  The circuit is the cascade of two differential pair amplifiers which is driven with a 10mV pp sine wave (page 1 of attached pdf).  Pnoise jitter simulation was run with the pnoise outputs take from the output of stage 1 and then run again with the pnoise outputs taken from the output of stage 2.  The schematic did not change between these two simulation runs.  I only changed the output nodes for pnoise analysis.  The result from the output of stage 1 was 5.8ps rms and the result from the output of stage 2 was 5.3ps rms (page 2 of attached pdf).  Two stages cascaded produces less jitter than the first stage which is obviously wrong.   Looking at the noise, it does increase from stage 1 to stage 2 but the slew rate increases faster and therefore the jitter is less.  

Hopefully I just have a setup problem (input.scs is page 3 of attached pdf).

Any comments or help would be appretiated.

Thanks,
Bryan