Hello all,

I have a huge mixed signal desing comprising of digital, analog and mixed-signal modules. The digital modules have
Verilog view, where as the others have schematic view. So I'm using SpectreVerilog. After setting up the hierarchy editor, when I try to simulate the design I get the following error:

USRERR: MS simulation does not support bidirectional interface element
                           generated by terminal pwrp of instance I135
                           in cellview (cell: ldod002_a1, lib: design_rajdeep, view: schematic)

Now what I tried and observed:

1. There are other bidirectional pins apart from the power pins. But no such error  for those pins. May be those errors were coming before the simulator stopped.

2. I cut two modules, both of them having bidirectional pins. Only one such error came about the pwrp (VDD) pin and then the simulation continued smoothly and finished perfectly!!! But there were other bidirectional pins. Only none of them were power pins.

Is it that too many of such errors are not avoidable by the simulator and it fails to proceed in case of the bigger design?
Why bidirectional pins are not allowed??? Or is there anything in the set up I'm missing?

Please help!
Rajdeep

Thanks a lot!! I'll try that out. But it's surprising to know the limitation of spectreVerilog!! Even big companies i know use spectreVerilog, I wonder how do they circumvent this problem. May be they make sure the bidirectional nets do not cross the analog/digital boundary.

Whatever it is ..thanx again!!

Rajdeep

Also you only have a2d and d2a interface elements along with spectreVerilog , there is no bidir interface elements in spectreVerilog.

This also explains why spectreVerilog does not support bidir connection cross the A/D boundary

Let me step in in this discussion, 'spectreVerilog' definitely
does not support bidirectional pins for mixed-signals between
analog to digital or digital to analog domains.
Otherwise the conversion of the signal with the a2d and d2a
interface elements would fail.

Maybe it helps to get a bit an insight on how interface elements work.
Interface elements are two terminal devices which are generated automatically
to connect analog to digital domains and translate signals between them and
vice versa.
Interface elements are associated with the input or output pins of digital components.

The a2d interface element will be inserted on a net between an analog output
and a digital input. Only state information will be passed to the digital domain.
The d2a interface element will be inserted on a net between an analog input
and a digital output. Voltage level information will be passed to the
analog domain, when the digital state changes.

The interface elements are only design to look at an output and translate
the incoming signal to a appropriate signal and pass this to the connected
input, nothing more. How should this concept be able to deal with bidirectional
signals?

This is handled differently in AMS Designer, where interface elements
were called connect module and are fully modelled with
Verilog AMS. In Verilog AMS it is possible to model such things
like bidirectional pins, because of the language capabilities.

Hope this helps to understand.

Bernd

Quote:

As I tried to explain for AMS designer connect modules were
modelled in Verilog AMS. Verilog AMS is a hardware description
language which has the capability to describe digital as well
as analog behaviour and bidirectional pins and internal signals.

e.g.  

connectmodule Bidir (Din, Aout);
 inout Din; logic Din;              // logic signal
 inout Aout; electrical Aout;      // electrical signal

Quote:


Honestly I don't know.

Bernd      

Actually you probably could do what Jonathan is suggesting using connect modules which use inherited connections - one signal can be directly connected, and the other can be located via an inherited connection (perhaps - I can't quite picture the situation that Jonathan is describing).

The thing to bear in mind though is that if you have two signals on the analog side, and one on the digital side, it doesn't really make sense to have automatic insertion of a connect module - because your circuit presumably needs to go through some kind of real life level shifter. You probably need to explicitly model the boundary in that case using a Verilog-AMS model.

Regards,

Andrew.

Rajdeep,
Sorry , I stongly suspect your magic here. Since SpectreVerilog does not have bidirection interface element. Theoritically it can NOT handle the bi-directional signal flow on Analog/Digital boundary

I guess ,  what you have done may change the A/D partition (spectreVerilog based on view name for partition) which could make your original bi-direction port no longer on A/D boundary . As I said before , spectreVerilog can perfectly handle bi-direction signal if it's not on A/D boundary.

Anyway, as long as you are happy with what you have changed , I am happy  :)
Zhong