Quote:Although could not understand why, rather how it is handled by AMS simulator undecided
As I tried to explain for AMS designer connect modules were
modelled in Verilog AMS. Verilog AMS is a hardware description
language which has the capability to describe digital as well
as analog behaviour and bidirectional pins and internal signals.
e.g.
connectmodule Bidir (Din, Aout);
inout Din; logic Din; // logic signal
inout Aout; electrical Aout; // electrical signal
Quote:Also, I have tried to run a simulation using spectreVerilog simualtor, there was one net pwrp that crossed the digital analog boundary. The simulator flagged one error also regarding this line, but continued to finish the simulation smoothly. How is it possible?
Honestly I don't know.
Bernd