Dear all,

consider an asynchronous div-by-N divider which is retimed by a FF. Assume the input of the divider is clocked at the positive edge of the incoming (clock) signal.

At which edge should the retiming FF be clocked? I would guess that the negative egde is the better choice
(robustness).

Further on: are there better retiming strategies or is the single FF most common?

Kind Regards

Peter

Dear mg777,

there is no clock recovery involved: it's just retiming of a divided CLK to minimize the jitter through accumulation by an asynchronous divider.

If the divider is triggered by pos edge of the input, I would think it is not save to trigger the retiming FF at the output by the same pos edge of the input, for reasons of FF set-up/hold time basically.

Kind Regards

Peter