Visjnoe
|
Dear mg777,
there is no clock recovery involved: it's just retiming of a divided CLK to minimize the jitter through accumulation by an asynchronous divider.
If the divider is triggered by pos edge of the input, I would think it is not save to trigger the retiming FF at the output by the same pos edge of the input, for reasons of FF set-up/hold time basically.
Kind Regards
Peter
|