Do a fundamental calculation before you start. The bandwidth of any amplifier cannot exceed gm/CL. If all of your 50 uA bias current was used in a BJT, the transconductance would be Ic/Vth = 2 mA/V at room temperature. With CL = 35 pF, this gives 60 Mr/s, less than 10 MHz. The transconductance of a FET is always lower than that of a BJT for the same bias current.

Your specifications are not realizable.

Vabzter,
I agree with the other posters -- it will be difficult to achieve that bandwidth with that load cap and total current.  

Here is how you can quickly see that by simply knowing that gm≈2*I/Vod, where Vod=Vgs-Vt if we are in strong inversion.  (In weak inversion gm≈ 2*I/(100mV); that is, you can't invcrease gm by making Vgs-Vt < 100mV).  

We know for a single stage amplifier (folded cascode, telescopic, etc), the bandwidth is gm/(2*pi*C) (where gm is 2*I/Vod of one side of the diff pair).  In this case, the required gm is (2*pi*10MHz)*35pF = 2.2mA/V.  Thus, we need a Vod=2*25uA/(2.2mA/V) = 23mV.  This is impossible - remember Vod limits to about 100mV when the devices get into subthreshold.

A more reasonable assumption of Vod=150mV limits your bandwidth to (2*25uA)/(2*pi*35pF*0.15) = 1.5MHz.  

Note I've assumed nothing about process.... just that gm ≈2*I/Vod, where Vod = Vgs-Vt in strong inversion, and 100mV in weak inversion.  

You can do a similar analysis for a two stage (e.g miller compensated) and show that your non-dominant pole will be around gm/Cload, so even if you can get the bandwidth, you won't have phase margin unless you put a zero in the system - which will create doublets (read Kameth, Grey, Meyer, "Relationship between frequency response and settling time of operation amplifiers," JSSC, Dec 1974).  While you can cheat a little here... you need to gain a factor of 10 in bandwidth.... I don't think you can do it and drive that load.

Rob

Hi Rob,
            Thanks for giving a simplified explaination..Well so I have formed new specs for the opamp.
Bw=1MHz,
Vout =1.7V,
Vdd=1.8V,
Idc(max)=50uA,
Cl=35pF,Rl=5Kohm,

So with these specs I tried to design a simple 2 stage opamp. I am getting an open loop gain of 40dB(very less). The phase margin is 80•.

My application is it should amplify the voltage at ouput of DAC whose full scale output is 1.2V.

So I am not getting whether I should use a 2 stage simple opamp of Cascode one..What is the criteria for selecting the topology?

Vabzter wrote on Feb 8^th, 2007, 7:23am:



I don't worry about those things...  You can do a lot by simply knowing that gm=2*I/Vod, where Vod=(Vgs-Vt).   You don't need to know what K' or Vt is to tune Vgs-Vt.... if it is too big, make the devices wider or lengths shorter.  You can get Vgs-Vt from the DC operating point information.  Vdsat is close to the same quantity -- it is what I usually look at.  Hand calculations that use more than Gm have limited use in the design process.... everything interesting is determined by parasitics or nonideal effects (plus Vt and K' change depending on operating point, sizes, etc).

Opamp design is pretty simple (ok, that is a gross exageration)....  You give the diff pair high gm, and the load (current mirror) low gm.  If you don't, you get a bad op-amp.  End of story .

For a given current, all you can do is change Vod.  150mV is a reasonable target for Vod for the diff pair.  Lower than that, the diff pair gets into weak inversion and wider widths offer only small improvements (i.e. diminishing returns).  2-400mV is a good target for the mirrors.  Since Vod =~ Vdsat, the upper limit is usually set by the amount of headroom you have.  

From that basic starting point you can play with the sizes to suit your particular situation (keeping current fixed and lengths as small as you can).  If your diff pair is causing frequency response problems you need to make it smaller, which will likely decrease gm (because Vod is increased).  Similarly, making the mirrors smaller (increasing Vod) will increase their frequency response (lower Cgs), but it may make other problems - like headroom or an inability to drive cap loads.  If you cannot fix things by changing Vod, your only other choice is to increase current (or change topologies).  

That said, the first thing I do when I get a new process is to plot the Vt vs. Width for various lengths of devices.  You get the Vt information from the DC operating point (just diode connect the devices and put 1uA thru them and do a parametric anlysis sweeping width and length).  You will find that Vt is a strong function of length and width for smaller geometries.  It is also instructive to plot gm/I vs Vgs-Vt for various sized devices, as well as Vt vs bulk-source voltage.  Armed with a few of these plots you can get most of the information you need.  Note that, in some sense, this is determining K' and other parameters, but since they are functinos of device sizes it put them in a more usable format.

rg