Hi

I am trying to find the input and output capacitance of a min size inverter for a 0.35um process. To find the input capacitance, I used the circuit as shown on the left of the attached picture. Voltage source V5 was ramped up from 0 to Vdd in a tranisent simulation. Since I=C(dv/dt), the graph of I/(dv/dt) was plotted against Vin to find C. The same method was used for the output cap except that 1G ohm resistors have been inserted at the rails to take care of the low resistance path provided by both rds resistors.

The ratio of output to input cap was found to be 2.8fF/2.0fF. May I know if this is actually possible? I thought that the gate capacitance is supposed to be the largest cap in the whole device.  :-? Is there anything wrong with the method which I have employed?

Thanks
Quek

The drain/source of the mos are the other terminals of the gate capacitance. In the circuit of the right, when the output voltage is low, looking into the drain of the NMOS you should have half of the capacitance seen when looking from the gate.

Than you must also add the capacitances from the PN junctions in the drain of both the PMOS and the NMOS transistors. The result is not very surprising for me,

Regards,
Humberto