Dear all,

when designing a PLL that uses a 'classical' 3-state PFD, the noise of the CP gets scaled by the ratio of the 'on-time' of the PFD and the period of the reference clock:

Code:

 Scp(f) = 2x 4kT.2/3.gm.(Ton/Tref)  

where the factor 2 accounts for the PMOS/NMOS contribution and their gm's are assumed to be equal for simplicity.

When implementing a CDR PLL using a Hogge PD, in 'locked-condition', both UP and DOWN are high for half of the bit period. To my opinion, this causes the noise of the CP to be scaled by 0.5 (except for feedback divider ratio) towards the PLL output:

Code:

 Scp(f) = 2x 4kT.2/3.gm.0.5 = 4kT.2/3.gm
 

So basically, the CP noise contribution is much larger in a CDR PLL using a Hogge PD than in a clock generation PLL using a 3-state PFD?

Is this observation correct?

Regards

Peter