dear all,

I  have ‘laid out’ this 8 bit processor in 180nm technology. Now I am designing a frequency synthesizer for  clock generation.  Following are the details

 
Reference Frequency = 100Mhz
VCO Frequency        =  800MHz
Divider Ratio             =  8

Loop filter design is problematic as i dont have software support for phase noise analysis of VCO and reference source. my earlier question was about any way which can help me estimate the phase noise without RF Spectre tyupe of softwares.
now i request anyone to share phase noise profiles of a ring oscillator designed in 180nm CMOS technology.

the point is, there should statistical simulated/measured profiles of phase noises for all the components of PLL for specific fabrication technologies.

this will great help people like me living in third world having very less resources at our disposal.

salman