Dear all,

I want to calculate the jitter of a kind of Delay Locked Loop (DLL). The design is driven by a 5MHz clock and is locked after about 7 us (tstab=20us for some safety). So, after reading some papers, I assume, that I have to set the Frequency Range in pnoise (and also within the Jee-Dialog) from about 1Hz to 2.5MHz. Is this assumption correct?

In some cadence-Handbook i read that the default number of sidebands is about 7. This number should be increased, until the calculated Jittervalues get constant. And here my problems begin:
I first set the sidebands in pnoise and the harmonics in pss to the same value. But than the Jittervalues are nearly chaotic within a range from 7 to 300 sidebands (=harmonics). I got the hint, that the harmonics influence the maxtimesteps and by this the accuracy of the whole design. So I set them to a fixed value of 150 and only vary the number of sidebands. Now the Jitter looks a bit like it could be assymptotic but a small positive gradient is left. So I have no idea of how to determine the jitter.

I would be thankful for every hint on this.

Greetings,
JitterGeorge

Thank you.
This paper gave me a very good insight into the theory.
The calculated jittervalues now seem to be suitable and nearly stable, after i calculated the desired sidebands to be nearly 1k.

So nice greetings till my next question  ;)

JitterGeorge

This depends on how much time you have  ;)

For 1k sidebands our sim-machine took about 9h. So for 8 corners you will need some time.
But I did some simulations with less sidebands and as it is written in Ken's Paper the error is quiet low even for only 100 sidebands (about 3%). So you will save 8 hours wich can be used for the corners.

Greetings,
George