Manish,

  If you have access to Cadence tools, in the ahdlLib are test
blocks for ADC INL and DNL. These blocks generate the test
signals and measure the INL/DNL. The default blocks are
for 8 bit converters, however, there are an internal variables
you can set for the current application.

`define NUM_ADC_BITS 12        was         8
`define NUM_OF_CODES 4096    was      256
`define NUM_OF_CONVS 16384  was     4096  

In addition, you will need to re-generate the symbol for 12-bits.
One additional comment, the simulation time can be long so
you probably want to combine the testbenches. Setup the simulations
for similar test conditions and only use one source to generate the
input signals. That is, you measure the INL and DNL from the same
stair case. One other option to speed-up the simulation it
to trade-off simulation time for resolution. The default number
of conversions is 16x times greater than the number of bits. If
you can live with 8x the number of steps, the simulation time
is twice as fast.

                                                    Best Regards,

                                                      Sheldon

Hi Sheldon:
   i have used some ahdl module ,but i can not netlist and run the adc_inl_ideal,please give me some advice.thanks!