Hi
I have a 2nd order sigma-delta (SD) design for digitally controlled oscillator (DCO). Also external dithering (of zero average value) is added to the input bits of this SD modulator. Please note that DCO is not present in my simulation. I just have ideal caps at the output of the SDM.

When I do a DC sweep of the input I got some non-linearity for the highest input (ie at the extreme end of the average o/p vs the input plot).
So upon investigation I found out the following:
1. When I turn external Dithering OFF this slight non-linearity goes away completely.
2. With dithering ON, the average value of carry output from the 1st order portion of the SDM is correct, i.e. in-different from the case of external dithering OFF.
3. Thus as expected, the second stage of the SDM o/p showed different average o/p (carry o/p) with external dithering.
4. I slowed down the reference and SDM clock by a factor of 10 and I still get poor result with external dither ON, and again from the second stage of the SDM.

When I look at the waveform I can't see any problem with adders when I have external dithering ON. I am trying pipelining next to the SDM to see if that resolves the issue. I would appreciate any feedback on this issue.
Thanks in advance.