Hello all,

this might be a trivial question but I was wondering how people go about checking whether there are no unintended connections in large designs.
Obviously, a "check and save" will reveal unconnected lines and also whether the signal lines have the same number of bits as the blocks their being routed to.

However, a "check and save" won't flag if I am using the same bus-bit for two blocks, ie. have signal<3> used on two different blocks by accident. Is there a way of checking whether each bit has only one connection?

Any tips on how people go about checking their top level schematic are appreciated.

Thanks,

Stefan wrote on Jun 20^th, 2008, 2:23am:


Thanks for the quick reply.

a) is out of the question as this is a full rf-receiver.
b) A LVS match will only tell if there's a mismatch between the layout and schematic, not if the schematic is connected correctly.

I'll see what I can do with the netlist.
At the moment I am relying on mixed-mode simulations to catch any wrong polarities or mis-connecitons. But this is more to verify the interaction between the digital control and the individual blocks. My verilogAMS views are not that detailed that they catch whether a current supply bias line has been used twice.

Cheers