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The Designer's Guide Community Forum › Design › Mixed-Signal Design › PLL settling time and lock time
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PLL settling time and lock time (Read 2472 times)
keikei
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PLL settling time and lock time
Jun 19th, 2008, 8:48am  
what is the difference between them?  or two expressions for the same concept?
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buddypoor
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Re: PLL settling time and lock time
Reply #1 - Jun 21st, 2008, 2:35am  
Itīs just a matter of definition; R.E. Best (Textbook: Phase-lock-loops) uses both names for the same parameter.
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LvW (buddypoor: In memory of the great late Buddy Rich)
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