Andrew Beckett
Senior Fellow
Offline
Life, don't talk to me about Life...
Posts: 1742
Bracknell, UK
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For a start, you'd need to escape the name because it has an exclamation mark in it - so it would be \vdd! ; (note the space before the semicolon - needed because an escape escapes everything up to the next space).
However, I don't understand why you're looking at a spectre netlist (input.scs) to find the syntax? AMS Designer can include spectre model files, but you're trying to connect (I assume) a global in a schematic netlisted for AMS Designer to the same signal in your Verilog-AMS code? If you're using AMS in ADE, you can look at the resulting schematic netlist. If using the hierarchy editor, you can look at the verilog.ams file in the schematic view in your library. Or you could just look at it in the simvision code browser.
There's no such thing as a global in Verilog, which is why the out of module reference approach is used.
Regards,
Andrew.
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