Pavel,

Globals get netlisted as an out of module reference in schematics - in the cds_globals module. If my memory is correct, it would end up as cds_globals.\gnd! (or something like that). Take a look at the netlist from a schematic containing gnd!, and you'll see the name used. Then you can use the same out of module reference in your verilogams code.

Regards,

Andrew.

For a start, you'd need to escape the name because it has an exclamation mark in it - so it would be \vdd! ; (note the space before the semicolon - needed because an escape escapes everything up to the next space).

However, I don't understand why you're looking at a spectre netlist (input.scs) to find the syntax? AMS Designer can include spectre model files, but you're trying to connect (I assume) a global in a schematic netlisted for AMS Designer to the same signal in your Verilog-AMS code? If you're using AMS in ADE, you can look at the resulting schematic netlist. If using the hierarchy editor, you can look at the verilog.ams file in the schematic view in your library. Or you could just look at it in the simvision code browser.

There's no such thing as a global in Verilog, which is why the out of module reference approach is used.

Regards,

Andrew.