I am using SpectreVerilog. If I use functional view for digital blocks, I got x state for all digital signal. If I use spectre model for all blocks (digital and analog), or use spectre model for some digital blocks, the simulation results are right. It seems like the timing is right only after binding some digital blocks to spectre model. I tried timescale of 10p/1p, 100p/1p, no different.

Can someone help me on this? thanks.

Thanks. I used the global timescale as you mentioned in the pdf file. There are many dff without RS in my circuit, which may cause the problem. Is there anyway to initilize them in spectreverilog? Thank you.

bernd wrote on Mar 2^nd, 2007, 3:13am: