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The Designer's Guide Community Forum › Measurements › Phase Noise and Jitter Measurements › input clock jitter
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input clock jitter (Read 2904 times)
sivacharan
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input clock jitter
Mar 06th, 2007, 2:01am  
Hi all,

My Q is regarding how can we specify input clock jitter in cadence?
Assume that i am using vpulse from analogLib as a clock.
I am unable to figure out where i can give the input clock jitter??

Thanks.
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Ken Kundert
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Re: input clock jitter
Reply #1 - Mar 6th, 2007, 9:48am  
The built-in sources do not implement jitter. You will need to use Verilog-A instead. Look on verilog-ams.com to find fixed-frequency oscillators (with and without jitter).

-Ken
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