Dear all,

I know that for a clock generation PLL the CP noise contribution towards to the output is scaled by the ratio of the on-time of the PFD and the reference period.

For a CDR (Clock and Data Recovery) PLL however, in the locked state both UP/DOWN pulses are high for half the clock period.

Can it therefore (as I assume) be concluded that the CP noise contribution is much higher (given the same current value) for a CP in a CDR PLL than in a clock generation PLL?
Consequently, is it true that the CP current should be typically much larger for a CDR PLL (for the same jitter)?

Regards

Peter