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Offstate transistor model (Read 2696 times)

ee484

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Offstate transistor model
Mar 09^th, 2007, 10:24am

Dear all,

What are the mechanisms that cause off-state finite resistance of MOS (i.e., NMOS)?

For example, a simple nmos switch case, is there any charges (i.e., intrinsic or induced charges when one of terminal is at high voltage (i.e.2V)) between source and drain? Can I assume that off-state finite resistance is mainly due to the resistance between two diffusions?

Or, another theory -The mainly responsible for off-state finite resistance of MOS is from the resistance between souce/drain and substrate contact. (Ptap for NMOS case, bulk contact).

any references and comments are welcome.

Last, but not least, can I trust spice for off-state mos model??

Best,
B

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Geoffrey_Coram

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Massachusetts, USA

Re: Offstate transistor model
Reply #1 - Mar 13^th, 2007, 7:28am

ee484 wrote on Mar 9^th, 2007, 10:24am:

Last, but not least, can I trust spice for off-state mos model??

This really is a question of whether you can trust your foundry to do an adequate job of extraction in subthreshold. I would expect that you can, particularly for digital designs, the off-state (subthreshold) leakage is of critical importance when you're trying to calculate the static power dissipation of your design.

If at first you do succeed, STOP, raise your standards, and stop wasting your time.

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