Suppose the CMOS switch resistor and sampling capacitor is constant and driving voltage source is ideal. And this S/H is intended for ADC.

Then the only error source for CMOS switch sample-hold circuit is linear settling (let's just forget about charge injection or feedthrough).

As long as above conditions are true, linear settling only scales the input a little bit by (1-exp(-ts/tau)) "tau=1/(Ron × Csamp)". And it will not introduce distortion or increase noise level. It only scales the signal gain a little bit.

My question is how is this linear settling error related with S/H or ADC's ENOB or Resolution. As we know ADC's ENOB is related with SNR which can be determined by FFT analysis.

But when we do the sampled voltage's FFT with linear settling error. It seems that it will not alter the result of SNR very much because no extra noise/distortion is added and it only scales the input a little bit.

I'm asking this because now I'm optimizing an cmos sampling switch for sigma-delta ADC with FFT analysis. Because I want to reduce charge injection indeced distortion. I have to reduce switch size. I want to know how small can I go for safety.

Anyone please help me!
Thank you very much.