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CDR Clock (Read 3047 times)
Amit Singh
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CDR Clock
Mar 19th, 2007, 12:05am  
Hi,
  I am working a Clock data recovery circuit at 6.5G in 0.18um tech. Do i need to saturate the clock after the VCO, or is it ok to feed the sine clock to the phase detector.

Thanks for the help,
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SATurn
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Re: CDR Clock
Reply #1 - Mar 21st, 2007, 10:28am  
Hello,

It depends on your PD topology. If it is based on SCL (source-coupled logic) topology, then it should be fine. Else, you are using CMOS gates in your PD, you should convert the levels to CMOS level.


SATurn
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