hi,everybody. I'm looking for help~~
There's a troublesome situation bothering me.
Because of the strange design of system, the input signal arrive at my chip before the chip power on.
Which means that the voltage of input pad is 5V but VDD pad is 0.
And then,obviously,a huge current occurs because the ESD PMOS turn on.
As a result,the parastic PNPs turn on and cause the latchup!!!

If I insert a 500 ohm resistor between pad and ESD PMOS, this problem will be solved. But hurt the data rate.
A kind professor suggest me that use "floating Nwell" to solve this problem but it  make the latchup immunity somewhat worse .

So, would you please help me to fight this problem?

thanks~