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dandelion

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A question on the current mirror
Mar 16^th, 2007, 11:01pm

hi,
Pls. take a look at the attached diagram of a current mirror.

This is a 1:100 current mirror. The NMOS CAP is added here to keep the gate from rippling. In designing/simulation, it is OK. The current ratio is good for all the PVT corners.

But the silicon test is disillusionary. The ratio of current mirror have large excursion from the design value. It is about only 1:80, when the input current is samll, the ratio of current mirror is even low to 1:60.

Another interesting thing is that the ratio of the current mirror have a positive linearly temperature coeffcients.I.e, when the temperature increases, the ratio increased also. While in simulatiion, it is independed with the temperature.

Would anyone help to find any issues with my circuit?

BTW, the process is 0.5um CMOS processs.
Thanks in advance

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MIRROR.jpg

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mg777

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Re: A question on the current mirror
Reply #1 - Mar 17^th, 2007, 7:52am

1. What is the substrate bias in your measurements? How are you forcing I_in and measuring I_out - using a SMU?

2. What are the source voltages of the two top transistors?

3. Are the devices drawn 0.6 μm supposed to be min length?

4. Plot (sim & meas) Fig. 4.9(b) on p 267 of Gray, Hurst, Lewis, & Meyer (4th ed).

M.G.Rajan
www.eecalc.com

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ywguo Community Fellow Offline Posts: 943 Shanghai, PRC	Re: A question on the current mirror Reply #2 - Mar 18^th, 2007, 11:17pm Hi, dandelion, Have you measure the voltage at the drain of the top transistor in the input branch? Thanks Yawei
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dandelion

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Re: A question on the current mirror
Reply #3 - Mar 19^th, 2007, 2:37am

mg777 wrote on Mar 17^th, 2007, 7:52am:

1. What is the substrate bias in your measurements? How are you forcing I_in and measuring I_out - using a SMU?

2. What are the source voltages of the two top transistors?

3. Are the devices drawn 0.6 μm supposed to be min length?

4. Plot (sim & meas) Fig. 4.9(b) on p 267 of Gray, Hurst, Lewis, & Meyer (4th ed).

M.G.Rajan

www.eecalc.com

Hi mg777,
Thanks for the reply.

The sub is connected to the GND.There is no sub pin in my chip.

In simulation, the source voltage have no mcuh difference and the match is good.But the test gives much descranpancy.

yes, it is the minimum length.

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monte78

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Re: A question on the current mirror
Reply #4 - Mar 19^th, 2007, 8:43am

I found the following data for the minimu channel length variation in a 0.6um CMOS technology:

Min = 0.43 um Typ =0.6 um Max 0.67 um

Now if you consider the worst case you will have:

ratio mirror * 0.43/0.67 = 100 * 0.43/0.67 = 64

This variation could explain your measurements. Probably, increasing your minimu channel length will improve dramatically your current mirror ratio.
What about your technology minimum length variations?

dandelion wrote on Mar 19^th, 2007, 2:37am:

mg777 wrote on Mar 17^th, 2007, 7:52am:

1. What is the substrate bias in your measurements? How are you forcing I_in and measuring I_out - using a SMU?

2. What are the source voltages of the two top transistors?

3. Are the devices drawn 0.6 μm supposed to be min length?

4. Plot (sim & meas) Fig. 4.9(b) on p 267 of Gray, Hurst, Lewis, & Meyer (4th ed).

M.G.Rajan

www.eecalc.com

Hi mg777,
Thanks for the reply.

The sub is connected to the GND.There is no sub pin in my chip.

In simulation, the source voltage have no mcuh difference and the match is good.But the test gives much descranpancy.

yes, it is the minimum length.

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chase.ng

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penang/malaysia

Re: A question on the current mirror
Reply #5 - Mar 20^th, 2007, 12:39am

The ratio of 1:100 seems very large to me, could it be the distance from the reference leg to the furthest leg in the current mirror is too large for them to track each other very well?

Also I would like to seek some opinion here, will it be better to build a current mirror with 1:100 ratio, or to build 2 current mirrors with ratio of 1:10 and then cascading them? It seems to me that it is easier to match the later.

Thanks and Regards,
Chase.

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Chase

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