dgFL2007
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Hi, all, I am new to here and I am not sure the same topic being brought up before. If so, please refer me to any similar topic on this forum.
I am designing a PLL right now and try to simulate the PFD/CP for its noise contribution. I had two ways. First method: Runing a small signal noise simulation when the charge pump is constantly on to get the output current noise POWER density (in A2/Hz), scale it with the actual duty cycle of the PFD/CP when the PLL is in lock condition, divided it by the PFD/CP gain which is Icp/2π to convert to PFD input refered inband noise floor. (There should be a scale factor of 2 somewhere to account for Single Side Band noise floor). Second method is from the document "Predicting the phase noise and jitter of PLL based frequency synthesizers, ver 4g" by Ken Kundert on this website. It is to run a pnoise simulation and to get the PFD/CP output current noise floor and directly converting it back to the PFD input refered noise floor by following equation 57 and 58 on page 30 of 51. My problem is that this two method give me different results, methods 2 seems provides very optimitic results on the noise floor (By 10+dB). After carefully inspecting noise contribution table and checking the component contributing flicker noise, it seems to me that pnoise simulation scale the charge pump output current noise with the duty cycle factor instead of the current noise power as in method one. I myself is confused on this and I am wondering anyone here has an answer on this? (It seems that method one gives me a resutls that matche the measurement)
So my questions is if I am using small signal noise to simulate PFD/CP, should I scale the duty cycle factor with the charge pump output current noise (method 2) or current noise sqared (method 1).
BTW, the duty cycle I mentioned above is that the PFD has a small reset time ΔT (which is to help remove PFD-deadzone) and the duty cycle factor is ΔT/Tref, in which Tref is the reference period at the PFD input.
Thanks, dgFL2007
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