sheldon
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Kim57,
Could you provide any additional information about your circuit? For example,
1) What does not work mean? is the circuit turned off, Ibias=0 does the block latch-up, Ibias=1A?
2) Does the band-gap reference include a start-up circuit?
3) Does the simulation include package parasitics?
4) Does the simulation include layout parasitics?
5) Are the transistors breaking down because the simulation is failing to converge?
6) Are you using core transistors, for example 1.2V transistors, in an I/O voltage application, 2.5V? So that if the circuit is not correctly biased the devices are in breakdown?
BTW, why do you need a 1ns start-up time for the band-gap reference? It seems a little fast.
These are just some suggestions to think about. However, in general the better you can describe the issue, the easier it will be for respond to you request with useful information.
Best Regards,
Sheldon
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