Hi, all.


I am currently doing layout for my chip.
As far as I know, I'd better place as many contacts as possible in the empty space in the chip so that they work as bypass capacitor.
Since I placed many contacts (for VSS and VDD), the signal wires have to run through these contacts. Of course, the signal path wires are MET2 and VSS and VDD underneath signal wires are MET1.

I am worrying anything below signal paths (in this case MET1 of VSS and VDD).

Please help me if you have any experience.

Another short question is if it is okay for a signal wire to run through VSS or VDD, then should I have to run a wire in parallel ? Or, it does not matter because VSS and VDD are DC.

Thank you all.

Hi,

What really a concern is the parasitic capacitance of signal path to ac gnd. Normally you would like to minimized them at all cost. Running signal in parallel with power will create large parasitic capacitance and should be avoided unless you need sheilding.

Do you mean you put a lot of substrate contacts?

Regards,
chase

My rule of thumb is to fill all of the empty space with substrate ties to improve latchup.  Sub-ties are not just contact alone but contact+pdiff assuming a p-substate process.  This is done at the block level.  At the chip level, empty spaces are filled with caps, perhaps mos caps.  

cheers,
LL