ee484
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Posts: 7
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Hi, all.
I am currently doing layout for my chip. As far as I know, I'd better place as many contacts as possible in the empty space in the chip so that they work as bypass capacitor. Since I placed many contacts (for VSS and VDD), the signal wires have to run through these contacts. Of course, the signal path wires are MET2 and VSS and VDD underneath signal wires are MET1.
I am worrying anything below signal paths (in this case MET1 of VSS and VDD).
Please help me if you have any experience.
Another short question is if it is okay for a signal wire to run through VSS or VDD, then should I have to run a wire in parallel ? Or, it does not matter because VSS and VDD are DC.
Thank you all.
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