Why most analog designers work bottom up with top down in mind?
It is the only way it works. If designers start bottom up they still have the topdown model in mind. And sometimes much better they leave the topdown model more vague in there minds if the bottom outcome could impact the topdown model more serious.
The hierarchical workflow creates the need for design contracts in an executable way. The model improve sometimes the understanding of the bottom design, or to be more specific, creates a more abstract view of the bottom up designed circuit. So there is a clear explanation why designers are so resistible to topdown methods. They are not needed for there own work responsibility. The models are needed for the hierarchical workflow. And the bad stuff about that is that analog creativity and perfection is rare and writing numerical accurate models exceeds often the capabilities of otherwise good designers.
Why do not others, I like to say model consumers, within the workflow, write the models. I imagine models which are ready after engineering samples.
Take an example: A complex analog baseband filter before the ADC in a receive path. With 4 programmable bandwidth settings and a calibration unit. If this filter model should give frequency depend noise response, EVM contribution, alternate channel blocking performance, matching depend supply rejection, ... it could be an endless list, model creation and verification effort higher than the circuit design effort.
Or lets say in much more cynical way. The schematic is the model!
If the model of the filter is only the s-function, what is the purpose of the model? The model consumers want all relevant effects which make an impact on interconnecting models or the performance contribution. But things which pop up in interconnecting circuit does not pop up by interconnecting models if the source of this verification surprise is not foreseen in the model! That is the reason why Spice is also needed for higher, in most cases toplevel verification too.
So the general answer is model consumers should write models as executable specification, circuit designers write there own model, the schematic. Hierarchical model verification is limited to things which are known in advance, verification is to cover also the unknown. Writing models could be a good learning exercise for model consumers honoring the effort of writing simpler models, the schematic.
Finally both is needed! More Spice and more models. The first to verify on the models closest to the physics, second to specify and communicate on the next level and only partly verify model interconnection on base of effects which you already know about.