What are the methods for reducing the integer boundary spurs in a Frac N synthesizer?

(Spurs occuring when the fractional value is quite low)

The loop bandwidth cannot be changed due to settling time requirements.

The synthesizer architecture can be modified.

It is preferred not to change the reference frequency.

Any information on this topic would be appreciated.

Thanks!

Dear
I am a master student in KULeuven. I used your method for modelling of
noise in pll as a jitter. I want to simulate the jitter in hspice or
spectre. In the other words, how can I simulate the jitter and see the
power density of noise in the output of the close loop pll using spectre
or hspice.

thanks in advance

Mohammad Masoumi