Simulating ESD events can be very tricky and even misleading.

Questions to ask yourself when simulating ESD:
 1. Do I actually know what the failure limits are for my devices?  (What is published by foundaries as Max ratings are not necessarily, or better stated as 'rarely',  ESD failure limits).

2. Can I actually simulate my clamps?   If they are snapback based designs, unless you have built and validated special models or the foundary has done it for you (most do not), simulating these clamps is pointless.  You can however simulate active clamps 'IF' your current/voltage levels are within the modeling ranges of the devices.  If you have not validated the performance of your ESD clamps in silicon, I would alsmot say do not waste your time trying to do a system or chip level ESD simulation.  ESD puts devices into regions of operation that are never modeled, such as high carrier injection effects, spatial thermal effects, impact ionization, and a host of other 2nd, 3rd and so on order physics effects.

3.  Do I really know what current and voltages I should be simulating?
   500V CDM events can be anywhere from 5 to 12 amps depending on the part, 200V MM can be 3-5 amps and 2kV HBM is typically < 1.3A, but is not fixed.  So if you are uncertain what currents you can expect (and I have never known anyone who could predict it for a part with great confidence), this can dramatically impact your simulations.

4.  Finally, determining the number of power clamps and their placement is very dependent on the type of clamp, the type of ESD architecture and the surrounding circuitry that is being protected.  Are you using distributed clamps or a handful of lumped element clamps?
Example: For some of my designs using distributred clamps, I placed each clamp no further than 0.1 ohms distance between each clamp, but for another clamp on the same process I required 0.5 ohms between clamps and still with another clamp on the same process not more than 1 ohms between clamps.  It very much depends on the overall approach, there is no single answer or even guideline.

So how did I determine these values anyway, by building test structures and blowing them up.  In other words, experience and real silicon, because I have never been able to fully guarantee ESD performance before testing silicon.  Its the nature of the beast.  However simulation can help make intelligent guesses.

Your approach is appropriate if you can answer the above 4 questions with confidence.  Otherwise, I would lean on the side of caution and rather than figure out what the max resistance is that you can tolerate, simply look at your overall padring and determine how you can get in as many clamps as possible, distributed as evenly as possible, and placed uniformly in the padring, in such a manner that you do not grow your padring significantly or impact product performance.

Hopefully the engineer who designed your clamp can tell you what the spacing should be as they should have tested it in silicon before delivering to you.

Regards,
Stephen
www.srftechnologies.com