Hey guys,

I try to verify with a simple SH block the kT/C noise equation using PSS and PNoise analysis with SpectreRF.
I use a simple MOS switch and a 800fF capacitor, see attached file. (Thus I assume at room temperature 71.9uV noise.)

The switch has an on-resitance of <100Ohm.

I follow the guidelines in http://www.designers-guide.org/Analysis/sc-filters.pdf
I adjust the maxacfreq and nr of sidebands (200) such that the error is fairly small.

In order to get the sampled noise power I use the time domain Pnoise simulation as proposed.
But dependend on the switch resistance I got different noise voltages.

Typically I obtain 44-48uV instead of 72uV!?

Where is my mistake? What I have to change in the setup.

Thanks much for you help!
Friedel

PS I notice that if I decrease the cap size below a certain value ca. 50f Spectre terminates with an error!
See below!

......


Order  2 used in      54 subintervals.
Order  8 used in       3 subintervals.
Order 10 used in       1 subintervals.
Order 16 used in     314 subintervals.

Conv residual norm = 1.56e-06.
Conv solution-change norm in fdtd = 211e-09.
Number of refinements using multi-interval Chebyshev polynomial spectral algorithm = 1. Total steps = 5166

MIC-PSA finite-difference refinement finished, took 420 ms.

pss: The steady-state solution was achieved in 4 iterations.
Number of accepted pss steps = 5166.
Total time required for pss analysis `pss' was 2.86 s.


*************************************************************
Periodic Noise Analysis `pnoise': freq = (100 kHz -> 100 MHz)
*************************************************************
Using the operating-point information generated by PSS analysis `pss'.
Working on time-domain noise timepoint 1 of 1 (time=0).

Internal error found in spectre at freq = 100 kHz during PNoise analysis `pnoise'.  Please run `getSpectreFiles' or send the netlist, the spectre log file, the behavioral model files, and any other information that can help identify the problem to support@cadence.com.
   Assertion failed in file `qptv_qpnoise.c' at line 1471.
   Assertion failed.

Hi

I am just looking into these issues and came across your post. I did some theoretical stuff on this in the past. I don't want to work out how to write equations here, but I think the bottom line is the frequency response of your circuit is about 2GHz so you could try increasing the max freq from 100MHz to something much higher than 2GHz. I would be interested to know if that works.

Best regards

Graham

Setting maxacfreq=2000GHz does not actually cause Spectre to analyze up to 2000GHz. It just sets the timestep in the PSS analysis small enough so that the trailing PNoise analysis can analyze up to 2000GHz.

Perhaps you can simply post your example and we can try it. It is much easier to debug a specific example than it is trying to develop a list of all the possible things that could be going wrong in an example that we cannot see.

-Ken

Hi

You say "At least I could find out that if I change the the number of fingers/m factor but still get the same W,  
the noise changes." This would imply you are adding significant parasitic capacitance from the model, wouldn't it? You would have to add a massive 280fF to get the result of 62uV though.

regards

Graham

Hi Friedel

I was hoping that someone else would have tried it. I am not sufficiently familiar with SpectreRF to use it and have not the time to learn it; I can't really justify asking someone else to do it, although I'm interested to know the answer because my company does use it and relies on the results!

Giving this a bit more thought, with the setup you have half the time the cap is floating and half the time it is shorted to virtual ground by the on impedance of the transistor which is about 100 Ohms. The noise is being measured at low frequency (1kHz) so you will have half the time with an RMS noise value of 72uV and half the time with the resistor noise. Maybe the resistor noise will be higher than sqrt(4kTRf) because you may get noise folded down from 200MHz +/-1kHz, 600MHz +/-1kHz, etc. (If the clock was 200MHz - I don't remember what was in your deck). Ignoring this folding down makes the resistor noise negligible so then the net noise in a 1Hz band at 1kHz would be
sqrt[(72*72)/2] = 51uV.

I am not sure if the folding down of noise could increase the resistor noise so as to bring up the RMS level to 62uV but it may do. There may also be an extra contribution from 1/f noise.

In a practical circuit I guess you would be sampling the cap voltage in the opposite clock phase which would mean that 72uV would not be getting reduced whenever the clock is high.

I would be interested to know if this points in the right direction.

regards

Graham

Hey Frank,

thanks for the proposal.
I run the script in the original and I obtain exactly the same results as presented in the Ken's paper sc-filters.pdf.
Then I have modified the script, such that I replace the CMOS switch with a single NMOS device of my process and
adapte the supply voltage.
I use the same clk frequency and bandwidth!

The result is almost the same as before, approx 10%less noise, even if I increase the sidebands and maxacfreq.

At least both runs match!

Thanks
Friedel