Hi All,
   How do we calculate the decap value for a power rail.
RDV

Hi Ken,
  This pdf explains what is bypassing, decoupling and so on.
I wanted some analysis on this.
There is one more paper,
Decoupling capacitor calculation for cmos circuits    -by Smith. (currently unable to open it through ieee).
But I really wanted some analysis.
Just for example:
 Can I you the same old formula ,  
Q= C*V

 Let me know your comments
Thanks,
Raviraj

Raviraj, you are going to have to give a lot more info if you want a more specific answer... what is making the noise, digital? How fast is it... both clk and slew rates?

If you look at the digital guys, they have lots of things out there about calculating decap values.  If you look at the old DEC alpha, they said that if my total capacitance that is being moved on any clock cycle is C, then if I have 10C in decap, my supply can't droop more than 10%... there are loads of assumptions built into that statement about resistance has to not be a problem charging the caps and such. Now 10C seems like a lot, but notice that any cap that is not moving can contribute to that 10C total... like NWell to bulk and non switching lines, etc.
In deep sub micron people don't tend to add decap as much as possible because of the leakage power, ESD concerns, etc.  Then you have to be smarter about making sure the caps are just enough and are where you need them (hiding them all in a corner of the chip because you had some vacant space isn't  going to cut it)  

hope this gets you pointed in the right direction...

David