hi

I am working on optimizing the PLL For better jitterperformance.

Now the earliar simulated jitter values are well with in the boundary. How ever the measured (post silicon) jitter values are outside the required boundary.

Can any of you plsease tell me how I can tackle the "Schematic" to reduce the Jitter.
i am starting with VCO ( Current Starved).

Pls tell what might have went wrong here.

Also kindly tell me the procedure to measuer the periodic Jitter and Long term Jitter.

For jitter measurement on Silicon, you can use wavecrest jitter measuring instruments.