Quote:Can I think of static phase error as the equivalent of skew in a clock tree? Two signals, refclk & synthclk in this case, with a constant offset?
Yes
Quote:Will a pll have a relatively constant static phase error over a frequency range, or is it really a fixed time interval? If the latter, I'd expect the static phase error of the pll to increase with frequency, as the clock period gets smaller relative to the offset. Am I thinking about this right?
I also expect the static phase error to increase with refclk frequency.
Quote:How does deadband behave? I'm imagining the instantanious phase error would slowly increase until it bumps into the end of the deadband, where the PLL will give it a nudge and it will start drifting to the opposite side of the deadband, rattling back and forth so to speak. What sort of patterns might I see when measuring period or phase-error vs. time?
Whenever the PLL is in deadband, the phase error may increase/decrease depending upon the loop dynamics and the noise in the loop e.g. Power supply noise. However, the correction will only happen when the PLL gets out of this band. You may see a distributed pattern of phase error in deadband.