Do you know if there is already a thread for Verilog AMS Differential Amplifier behavioral modeling (especially for High-Speed CML logic gates)? I'm looking to write a set of such models (my previous CML behavioral models were purely Verilog-D) -- maybe with a compile-time switch between Verilog-D and Verilog-AMS.

http://www.designers-guide.org/Forum/YaBB.pl?num=1148909190 (Earlier thread about CML modeling ... not conclusive)