jhjones
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Texas Blacklands Prarie
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Do you know if there is already a thread for Verilog AMS Differential Amplifier behavioral modeling (especially for High-Speed CML logic gates)? I'm looking to write a set of such models (my previous CML behavioral models were purely Verilog-D) -- maybe with a compile-time switch between Verilog-D and Verilog-AMS.
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