ASCII art below shows an Alexander (bang-bang) phase detector as used in a CDR:

Din --->   (CLK) ----> QA ----> (CLK) ----> QB             UP = QB XOR QD

Din --->  (CLK/) ----> QC ----> (CLK) ----> QD            DOWN = QA XOR QD


1. What is the behavior under lock? My reasoning is: the CLK edges coincide with the rising edge of Din, so the 'dither' signal is caused by metastability of the first flip-flop in the top row. Does this make sense? If so, is it a statistically robust scheme from the viewpoint of a 'static' phase offset under lock?

2. Shouldn't the first flip-flop in the top row be master-slave? Else the second flop will try to latch on the same rising data edge.

3. I can see that the Alexander is insensitive to CLK-Q delay, but is it obvious that it will have a smaller data dependent jitter under lock? Has anyone walked an Alexander with static phase offsets and compared its DDJ with, say, a Hogge?

Any illumination/references welcome.

M.G.Rajan