The Designer's Guide Community
Forum
Welcome, Guest. Please Login or Register. Please follow the Forum guidelines.
Oct 31st, 2024, 5:46pm
Pages: 1
Send Topic Print
low voltage design technique (Read 999 times)
jeremy_zhu
New Member
*
Offline



Posts: 1
China
low voltage design technique
Jun 19th, 2007, 4:37am
 
   i'm trying to design a ultra-low voltage opa . the model i used to design it is a typical 0.5um CMOS model whose Vtn≈0.85(w/l 20/0.5) ,Vtp≈0.95(w/l 20/5.5), but my supply voltage is only sub-1v(0.9 or less). the opa must satisfy the specifications:>80dB 10~20Mhz GBW and constant gm with rail to rail ICMR. i want to know whether it can be realized for the model by some special technique :FG ,BULK-DRIVEN or some other ones.
any special comments ,suggestions or useful references?
Back to top
 
 
View Profile   IP Logged
carlgrace
Senior Member
****
Offline



Posts: 231
Berkeley, CA
Re: low voltage design technique
Reply #1 - Jun 27th, 2007, 5:30am
 
Bulk driven will be very hard to meet specs.  You will probably want to do a two stage op amp, with two input diff pairs, one is NMOS and one is PMOS.   A very good book to get started is Laker and Sansen.  You can also search for rail-to-rail input stages on Google.

good luck,
Carl
Back to top
 
 
View Profile   IP Logged
vivkr
Community Fellow
*****
Offline



Posts: 780

Re: low voltage design technique
Reply #2 - Jul 11th, 2007, 3:03am
 
jeremy_zhu wrote on Jun 19th, 2007, 4:37am:
   i'm trying to design a ultra-low voltage opa . the model i used to design it is a typical 0.5um CMOS model whose Vtn≈0.85(w/l 20/0.5) ,Vtp≈0.95(w/l 20/5.5), but my supply voltage is only sub-1v(0.9 or less). the opa must satisfy the specifications:>80dB 10~20Mhz GBW and constant gm with rail to rail ICMR. i want to know whether it can be realized for the model by some special technique :FG ,BULK-DRIVEN or some other ones.
any special comments ,suggestions or useful references?


Hi Jeremy,

While bulk-driven techniques may be not be optimal for your specs, you can certainly try to reduce the threshold voltages of your transistors by applying a
small forward-bias to the bulk-source junction. Needless to say, this is fraught with peril in case you latchup.

Regards
Vivek
Back to top
 
 
View Profile   IP Logged
JD
New Member
*
Offline



Posts: 1

Re: low voltage design technique
Reply #3 - Aug 20th, 2007, 3:21pm
 
No, it won't work unless you lower vtn and vtp. If your vdd < |vtn| + |vtp|, bulk driving maybe the only way to go.
Back to top
 
 
View Profile   IP Logged
Pages: 1
Send Topic Print
Copyright 2002-2024 Designer’s Guide Consulting, Inc. Designer’s Guide® is a registered trademark of Designer’s Guide Consulting, Inc. All rights reserved. Send comments or questions to editor@designers-guide.org. Consider submitting a paper or model.